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description the ADNS-2610 is a new entry level, small form factor optical mouse sensor. it is used to implement a non- mechanical tracking engine for computer mice. unlike its predecessor, this new optical mouse sensor allows for more compact and afordable optical mice designs. it is based on optical navigation technology, which mea - sures changes in position by optically acquiring sequential surface images (frames) and mathematically determining the direction and magnitude of movement. the sensor is housed in an 8-pin staggered dual inline package (dip). it is designed for use with the hdns-2100 lens, hlmp-ed80-xx000, and the hdns-2200 led clip, providing an optical mouse solution that is compact and afordable. there are no moving parts, so precision opti - cal alignment is not required, thereby facilitating high volume assembly. the output format is a two wire serial port. the current x and y information are available in registers accessed via the serial port. resolution is 400 counts per inch (cpi) with rates of motion up to 12 inches per second (ips). theory of operation the ADNS-2610 is based on optical navigation technol - ogy. it contains an image acquisition system (ias), a digi - tal signal processor (dsp) and a two wire serial port. the ias acquires microscopic surface images via the lens and illumination system provided by the hdns-2100, hdns-2200, and hlmp-ed80-xx000. these images are processed by the dsp to determine the direction and distance of motion. features ? precise optical navigation technology ? small form factor (10 mm x 12.5 mm footprint) ? no mechanical moving parts ? complete 2d motion sensor ? common interface for general purpose controller ? smooth surface navigation ? accurate motion up to 12 ips ? 400 cpi resolution ? high reliability ? high speed motion detector ? wave solderable ? single 5.0 volt power supply ? conforms to usb suspend mode specifcations ? power conservation mode during times of no movement ? serial port registers C programming C data transfer ? 8-pin staggered dual inline package (dip) applications ? mice for desktop pcs, workstations, and portable pcs ? trackballs ? integrated input devices ADNS-2610 optical mouse sensor data sheet
2 pinout of ADNS-2610 optical mouse sensor pin number pin description 1 osc_in oscillator input 2 osc_out oscillator output 3 sdio serial data (input and output) 4 sck serial port clock (input) 5 led_cntl digital shutter signal out 6 gnd system ground 7 vdd 5v dc input 8 refa internal reference figure 2. package outline drawing. figure 1. mechanical drawing: top view. 5 6 7 8 l e d _ c n t l g n d v d d r e f a s c k s d i o o s c _ o u t o s c _ i n 4 3 2 1 a 2 6 1 0 x y y w w z caution: it is advisable that normal static precautions should be taken in the handling and assembly of this component to prevent damage and/or degradation which may be induced by esd.
overview of optical mouse sensor assembly note: pin 1 of optical mouse sensor should be inserted into the reference point of mechanical cutouts. figures 3 and 4 are shown with hdns-2100, hdns-2200 and hlmp-ed80-xx000. avago technologies provides an iges fle drawing de - scribing the base plate molding features for lens and pcb alignment. the components shown in figure 5 interlock as they are mounted onto defned features on the base plate. the ADNS-2610 sensor is designed for mounting on a through hole pcb, looking down. there is an aperture stop and features on the package that align to the lens. the hdns-2100 lens provides optics for the imaging of the surface as well as illumination of the surface at the optimum angle. features on the lens align it to the sensor, base plate, and clip with the led. the lens also has a large round fange to provide a long creepage path for any esd events that occur at the opening of the base plate. the hdns-2200 clip holds the led in relation to the lens. the leds leads must be formed frst before inserting into the clip. then, both led and clip is loaded on the pcb. the clip interlocks the sensor to the lens, and through the lens to the alignment features on the base plate. the hlmp-ed80-xx000 is recommended for illumination. if used with the bin table (as shown in figure 8), sufcient illumination can be guaranteed. figure 5. exploded view drawing. figure . recommended pcb mechanical cutouts and spacing. h d n s - 2 2 0 0 ( c l i p ) h l m p - e d 8 0 - x x 0 0 0 a d n s - 2 6 1 0 ( s e n s o r ) c u s t o m e r s u p p l i e d p c b h d n s - 2 1 0 0 ( l e n s ) c u s t o m e r s u p p l i e d b a s e p l a t e w i t h r e c o m m e n d e d a l i g n m e n t f e a t u r e s p e r i g e s d r a w i n g figure 4. 2d assembly drawing of ADNS-2610 shown with the hlmp-ed80 (top and side view). base pla te plastic spring clip base pla te alignment post sensor pcb esd lens ring 7.45 0.293 32.46 1.278 19.10 0.752 13.82 0.54 4 10.58 0.417 14.58 0.574 dimensions in mm/in. +x +y (t op view) (side view) 29.15 all dimensions 0 1.148 11.10 0.437 12.60 0.496 1.25 0.049 mm inch 1.35 0.053 4.91 0.193 7.45 0.293 13.73 0.541 3.50 clear zone 0.138 28.00 1.102 18.94 0.746 1.00 0.039 9.06 0.357 0 8x 0.80 0.031
4 pcb assembly considerations 1. insert the sensor and all other electrical components into pcb. note: pin 1 of the sensor should always be the reference point of mechanical cutouts. 2. bend the led leads 90 and then insert the led into the assembly clip until the snap feature locks the led base. 3. insert the led/clip assembly into pcb. 4. wave solder the entire assembly in a no-wash solder process utilizing solder fxture. the solder fxture is needed to protect the sensor during the solder process. the fxture should be designed to expose the sensor leads to solder while shielding the optical aperture from direct solder contact. the solder fxture is also used to set the reference height of the sensor to the pcb top during wave soldering (note: do not remove the kapton tape during wave soldering). 5. place the lens onto the base plate. 6. remove the protective kapton tape from optical aper - ture of the sensor. care must be taken to keep contami - nants from entering the aperture. it is recommended not to place the pcb facing up during the entire mouse assembly process. the pcb should be held vertically for the kapton removal process. 7. insert pcb assembly over the lens onto the base plate aligning post to retain pcb assembly. the sensor ap - erture ring should self-align to the lens. 8. the optical position reference for the pcb is set by the base plate and lens. note that the pcb motion due to button presses must be minimized to maintain optical alignment. 9. install mouse top case. there must be a feature in the top case to press down onto the clip to ensure all components are interlocked to the correct vertical height. figure 6. block diagram of ADNS-2610 optical mouse sensor. design considerations for improving esd performance the fange on the lens has been designed to increase the creepage and clearance distance for electrostatic discharge. the table below shows typical values assuming base plate construction per the avago supplied iges fle and hdns-2100 lens fange. typical distance millimeters creepage 16.0 clearance 2.1 for improved esd performance, the lens fange can be sealed (i.e. glued) to the base plate. note that the lens material is polycarbonate and therefore, cyanoacrylate based adhesives or other adhesives that may damage the lens should not be used. sc k sdio seria l por t serial port image processo r led control led control oscilla to r resona to r osc_in osc_out re fa vol t age regula tor and power control v dd gnd vol t age reference 5 vol t power pcb sensor led base plate lens/light pipe clip surface figure 7. sectional view of pcb assembly highlighting optical mouse components (optical mouse sensor, clip, lens, led, pcb and base plate).
5 figure 8. circuit block diagram for a typical corded optical mouse using an avago ADNS-2610 optical mouse sensor. 6 m h z ( o p t i o n a l ) 1 0 9 p 0 . 7 p 0 . 6 x t a l i n x t a l o u t d + d - v r e g p 1 . 0 p 1 . 1 p 0 . 0 v p p v d d g n d v d d s d i o s c k l e d _ c n t l s u r f a c e 1 k o h m s 1 0 0 k o h m s r 1 2 n 3 9 0 6 h d n s 2 1 0 0 l e n s i n t e r n a l i m a g e s e n s o r h l m p - e d 8 0 - x x 0 0 0 o s c _ i n c e r a m i c r e s o n a a t o r m u r a t a c s a l s 2 4 m 0 x 5 3 - b 0 t d k f c r 2 4 . 0 m 2 g 2 . 2 f 2 4 m h z o s c _ o u t r e f a 7 1 3 8 5 1 4 1 1 2 v d d d + d - g n d g n d 1 . 3 k 0 . 1 f 4 . 7 f 0 . 1 f q a q b v d d r z l e d s h l d v d d 1 1 v s s c y p r e s s c y 7 c 6 3 7 2 3 c - p c a d n s - 2 6 1 0 p 0 . 5 1 7 6 5 1 2 8 7 3 4 1 6 1 5 p 0 . 3 p 0 . 2 p 0 . 1 4 3 2 6 l m r b u t t o n s r 1 v a l u e ( o h m s ) 3 2 . 0 3 2 . 0 3 2 . 0 3 2 . 0 3 2 . 0 t o 6 1 . 2 3 2 . 0 t o 7 3 . 9 3 2 . 0 t o 8 4 . 4 3 2 . 0 t o 1 0 3 3 2 . 0 t o 1 3 0 k l m n p q r s t h l m p - e d 8 0 b i n notes on bypass 6, 7 and 6, 8 capacitors ? caps for pins 6,7 and 8 to ground must have trace lengths less than 5 mm. ? the 0.1 uf caps must be ceramic. ? caps should have less than 5 nh of self inductance ? caps should have less than 0.2 ohms esr ? surface mount parts are recommended regulatory requirements ? passes fcc b and worldwide analogous emission limits when assembled into a mouse with unshielded cable and following avago recommendations. ? passes en61000-4-4/iec801-4 eftb tests when assem - bled into a mouse with shielded cable and following avago recommendations. ? ul fammability level ul94 v-0. ? provides sufcient esd creepage/clearance distance to avoid discharge up to 15 kv when assembled into a mouse according to usage instructions above. ? for eye safety consideration, please refer to the tech - nical report available on the web site at www.avago. com/semiconductors.
6 absolute maximum ratings parameter symbol minimum maximum units notes storage temperature t s -40 85 c operating temperature t a -15 55 c lead solder temp 260 c for 10 seconds, 1.6 mm below seating plane supply voltage v dd -0.5 5.5 v esd 2 kv all pins, human body model mil 883 method 3015 input voltage v in -0.5 v dd +0.5 v sdio, clk, led_cntl input voltage v in -0.5 3.6 v osc_in, osc_out, refa recommended operating conditions parameter symbol minimum typical maximum units notes operating temperature t a 0 40 c power supply voltage v dd 4.1 5.0 5.5 volts register values retained for voltage transients below 4.10v but greater than 3.9v power supply rise time v rt 100 ms supply noise v n 100 mv peak to peak within 0-100 mhz bandwidth clock frequency f clk 23.0 24.0 25.0 mhz set by ceramic resonator serial port clock frequency sclk f clk /12 mhz resonator impedance x res 55 distance from lens z 2.3 2.4 2.5 mm results in 0.2 mm dof reference plane to surface (see figure 9) speed s 0 12 in/sec @ frame rate = 1500 fps acceleration a 0.25 g @ frame rate = 1500 fps light level onto ic irr inc 80 25,000 mw/m 2 = 639 nm 100 30,000 = 875 nm sdio read hold time t hold 100 s hold time for valid data (refer to figure 22) sdio serial t sww 100 s time between two write commands write-write time (refer to figure 25) sdio serial t swr 100 s time between write and read write-read time operation (refer to figure 26) sdio serial t srw 250 ns time between read and write read-write time operation (refer to figure 27) sdio serial t srr 250 ns time between two read commands read-read time (refer to figure 26) data delay after t compute 3.1 ms after t compute , all registers contain pd deactivated data from frst image after wakeup from power-down mode. note that an additional 75 frames for agc stabilization may be required if mouse movement occurred while power down. (refer to figure 10) sdio write setup time t setup 60 ns data valid time before the rising of sclk (refer to figure 20) frame rate fr 1500 frames/s
7 figure 9. distance from lens reference plane to surface. ac electrical specifcations electrical characteristics over recommended operating conditions. typical values at 25c, v dd = 5 v, 24 mhz, 1500 fps. parameter symbol min. typ. max. units notes power down (pd) t pd 1.33 s 32 clock cycle minimum after setting bit 6 in the confguration register.(refer to figure 12) power up after pd mode t pupd 50 ms from pd mode deactivation to accurate deactivated reports 610 s + 75 frames (refer to figure 10). power up from v dd t pu 40 ms from v dd to valid accurate reports 610 s + 50 frames rise and fall times sdio t r 30 ns c l = 30 pf (the rise time is between 10% to 90%) t f 16 ns c l = 30 pf (the fall time is between 10% to 90%) serial port transaction timer t sptt 90 ms serial port will reset if current transaction is not complete within t sptt (refer to figure 29). transient supply current i ddt 20 37 ma max supply current during a v dd ramp from 0 to 5.0v with > 500 ms rise time. does not include charging current for bypass capacitors. adns-261 0 hdns-2100 z object surf ace
8 dc electrical specifcations electrical characteristics over recommended operating conditions. typical values at 25c, v dd = 5 v, 24 mhz, 1500 fps. parameter symbol min. typ. max. units notes supply current (mouse moving) i dd avg 15 30 ma supply current (mouse not moving) i dd 12 ma power down mode current i ddpd 170 230 a sck pin input low voltage v il 0.8 v input high voltage v ih 2.0 v input capacitance c in 10 pf input resistance r in 1 m sdio pin v dd = 4v, load = 50 pf, 80 ns rise & fall input low voltage v il 0.8 v input high voltage v ih 2.0 v output low voltage v ol 0.5 v output high voltage v oh 0.8 * v dd v drive low current i l 2.0 ma drive high current i h 2.0 ma input capacitance c in 10 pf input resistance r in 1 m led_cntl pin output low voltage v ol 0.1 v output high voltage v oh 0.8 * v dd v drive low current i l 250 a drive high current i h 250 a osc_in input resistance r in 500 k input capacitance c in 15 pf input high voltage v ih 2.2 v external clock source input low voltage v il 0.8 v external clock source
9 pd pin timing note: all timing circuits shown, from figure 10 onwards, are based on the 24 mhz resonator frequency. figure 10. power up timing mode. figure 11. details of wake-up timing after pd. i dd power down deactivation power down deactivated (610) s t compute (see figure 11 ) t pupd 75 frames led current oscillator start power down deactivation power down deactivated 250 s reset count 360 s initialization new acquisition 2410 s sck optional spi transactions with old image dat a 610 s t comput e spi transactions with new image data at default frame rate
10 power-down mode (pd) and timing ADNS-2610 can be placed in a power-down mode by setting bit 6 in the confguration register via a serial i/o port write operation. note that while writing a 1 to bit 6 of the confguration register, all other bits must be writ - ten with their original value in order to keep the current confguration. after setting the confguration register, wait at least 32 system clock cycles. to get the chip out of the power-down mode, clear bit 6 in the confguration register via a serial i/o port write operation. (caution! in power-down mode, the spi timeout (t sptt ) will not func - tion. therefore, no partial spi command should be sent. otherwise, the sensor may go into a hang-up state). while the sensor is in power-down mode, only the bit 6 data will be written to the confguration register. writing the other confguration register values will not have any efect. for an accurate report after power-up, wait for a total period of 50 ms before the microcontroller is able to issue any write/read operation to the ADNS-2610. the sensor register settings, prior to power-down mode, will remain during power-down mode. figure 1 . power-down confguration register writing operation. setting the power down bit simply sets the analog circuitry into a no current state. note: led_cntl, and sdio will be tri-stated during power down mode. figure 12. power-down timing. the address of the configuration register is 0000000. assume that the original content of the confguration register is 0x00. clk sck sdio i dd 32 clock cycles min 1 a 6 a 5 a 4 a 3 d 5 d 4 d 3 d 2 d 1 d 0 t pd configuration register address 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 configuration register data writ e sck sdio operation
11 typical performance characteristics performance characteristics over recommended operating conditions. typical values at 25c, v dd = 5 v, 24 mhz, 1500 fps. parameter symbol min. typ. max. units notes path error (deviation) p error 0.5 % path error (deviation) is the error from the ideal cursor path. it is expressed as a percentage of total travel and is measured over standard surfaces. the following graphs (figures 14-18) are the typical per - formance of the ADNS-2610 sensor, assembled as shown in the 2d assembly drawing with the hdns - 2100 lens/ prism, the hdns-2200 clip, and the hlmp-ed80-xx000 (see figure 4). z (mm) figure 14. typical resolution vs. z (comparative surfaces) dpi -1 500 400 300 200 100 0 -0.8 -0.6 -0.4 -0.2 -0 0.2 0.4 0.6 0.8 1 burl formica white paper manila black copy black walnut velocity (ips) figure 15. typical resolution vs. velocity @ 1500 fps. dpi 1 500 400 300 200 100 0 3 5 7 9 11 13 15 white paper manila black copy wavelength (nm) relative responsivity 400 100 0 700 500 900 800 600 1.0 0.8 0.6 0.4 0.2 0 figure 16. wavelength responsivity [1] . notes: 1. the ADNS-2610 is designed for optimal performance when used with the hlmp- ed80-xx000 (red led 639 nm). for use with other led colors (i.e., blue, green), please consult factory. when using alternate leds, there may also be performance degradation and additional eye safety considerations. 2. z = distance from lens reference plane to surface. 3. dof = depth of field. z (mm) figure 17. typical resolution vs. height at different led current levels on manila folder. dpi -1 500 400 300 200 100 0 -0.6 -0.2 0.2 0.6 1 100% 75% 50% z (mm) figure 18. typical resolution vs. height at different led current levels on black copy. dpi -1 600 500 400 300 200 100 0 -0.6 -0.2 0.2 0.6 1 100% 75% 50%
12 figure 19. write operation. synchronous serial port the synchronous serial port is used to set and read param - eters in the ADNS-2610, and also to read out the motion information. the port is a two wire, half duplex port. the host micro - controller always initiates communication; the ADNS-2610 never initiates data transfers. sck : the serial port clock. it is always generated by the master (the microcontroller). sdio : the data line. write operation write operations, where data is going from the micro - controller to the ADNS-2610, is always initiated by the microcontroller and consists of two bytes. the frst byte contains the address (seven bits) and has a 1 as its msb to indicate data direction. the second byte contains the data. the transfer is synchronized by sck . the microcontroller changes sdio on falling edges of sck . the ADNS-2610 reads sdio on rising edges of sck. sck sdi o sdio driven by microcontrolle r 1 a 6 a 5 a 4 a 3 a 2 a 1 a 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 sck cycle # don' t care figure 20. sdio setup and hold times sck pulse width. sck sdio t set u p = 60 ns, min 250 ns, min 250 ns 250 ns
1 note: the 250 ns high state of sck is the minimum data hold time of the adns- 2610. since the falling edge of sck is actually the start of the next read or write command, the ADNS-2610 will hold the state of d 0 on the sdio line until the falling edge of sck. in both write and read operations, sck is driven by the microcontroller. read operation a read operation, meaning data that is going from the ADNS-2610 to the microcontroller, is always initiated by the microcontroller and consists of two bytes. the frst byte that contains the address is written by the microcon - troller and has a 0 as its msb to indicate data direction. the second byte contains the data and is driven by the ADNS-2610. the transfer is synchronized by sck . sdio is changed on falling edges of sck and read on every rising edge of sck . the microcontroller must go to a high-z state after the last address data bit. the ADNS-2610 will go to the high-z state after the last data bit. another thing to note during a read operation; sck needs to be delayed after the last address data bit to ensure that the ADNS-2610 has at least 100 s to prepare the requested data. this is shown in the timing diagrams below (see figures 21 to 23). figure 21. read operation. sdio driven by microcontrolle r sdio driven by ADNS-2610 1 2 3 4 5 6 7 8 sck cycle # sck sdi o 0 a 6 a 5 a 4 a 3 a 2 a 1 a 0 d 6 d 5 d 4 d 3 d 2 d 1 d 0 d 7 9 10 11 12 13 14 15 16 detail "a" detail "b " 250 ns, max microcontrolle r to ADNS-2610 sdio handof f detail "a" a 0 250 ns, mi n sck sdi o hi-z 0 ns, mi n a 1 250 ns, max d 7 160 ns, mi n d 6 60 ns, mi n t hold 100 s, min ADNS-2610 to microcontrolle r sdio handof f detail "b" sck sdi o 250 ns, mi n d 0 160 ns, max r/w bit of next addres s released by ADNS-2610 driven by microcontrolle r figure 22. microcontroller to ADNS-2610 sdio handof. figure 2 . ADNS-2610 to microcontroller sdio handof.
14 figure 24. sdio hi-z state and timing. forcing the sdio line to the hi-z state there are times when the sdio line from the ADNS-2610 should be in the hi-z state. for example, if the micropro - cessor has completed a write to the ADNS-2610, the sdio line will go into a hi-z state, because the sdio pin was confgured as an input. however, if the last operation from the microprocessor was a read, the ADNS-2610 will hold the d0 state on sdio until a falling edge of sck. to place the sdio pin into a hi-z state, activate the power- down mode by writing to the configuration register. then, the power-down mode can stay activated, with the ADNS-2610 in the shutdown state, or the power-down mode can be deactivated, returning the ADNS-2610 to normal operation. in both conditions, the sdio line will go into the hi-z state. sdi o 10 ns, ma x pd activated hi-z 32 clock cycles pd timing
15 figure 26. timing between write and read commands. figure 27. timing between read and either write or subsequent read commands. if the rising edge of sck for the last address bit of the read command occurs before the 100 microsecond required de - lay, then the write command may not complete correctly. the falling edge of sck for the frst address bit of either the read or write command must be at least 250 ns after the last sck rising edge of the last data bit of the previous read operation. required timing between read and write commands (tsxx) there are minimum timing requirements between read and write commands on the serial port. if the rising edge of the sck for the last data bit of the second write command occurs before the 100 microsec - ond required delay, then the frst write command may not complete correctly. figure 25. timing between two write commands. sck address data t sww 100 s write operation address data write operation sck address data write operation address next read operation t swr 100 s data t 1 100 s address t srw and t srr >250 ns next read or write operation address sck read operation
16 error detection and recovery 1. the ADNS-2610 and the microcontroller might get out of synchronization due to esd events, power supply droops or microcontroller frmware faws. 2. the ADNS-2610 has a transaction timer for the serial port. if the sixteenth sck rising edge is spaced more than approximately 90 milliseconds from the frst sck edge of the current transaction, the serial port will reset. 3. invalid addresses: C writing to an invalid address will have no efect. reading from an invalid address will return all ze - ros. 4. collision detection on sdio C the only time that the adns - 2610 drives the sdio line is during a read operation. to avoid data collisions, the microcontroller should relinquish sdio before the falling edge of sck after the last address bit. then the ADNS-2610 begins to drive sdio after the next rising edge of sck. next, the adns - 2610 relinquishes sdio within 160 ns of the falling sck edge after the last data bit. the microcontroller can begin driving sdio any time after that. in order to maintain low power consumption in normal operation or when the pd bit is set high, the microcontroller should not leave sdio foating until the next transmission (although that will not cause any communication difculties). 5. in case of synchronization failure, both the ADNS-2610 and the microcontroller may drive sdio. the adns- 2610 can withstand 30 ma of short circuit current and will withstand infnite duration short circuit condi - tions. 6. the microcontroller can verify a successful write opera - tion by issuing a read command to the same address and comparing the written data to the read data. 7. the microcontroller can verify the synchronization of the serial port by periodically reading the product id from status register (address: 0x01). figure 28. power-up serial port sequence. data 0x0b000xxxxx address 0x01 sck sdio v dd problem area notes on power-up and the serial port the sequence in which v dd , sck and sdio are set during powerup can afect the operation of the serial port. the diagram below shows what can happen shortly after powerup when the microprocessor tries to read data from the serial port. this diagram shows the v dd rising to valid levels, at some point the microcontroller starts its program, sets the sck and sdio lines to be outputs, and sets them high. then, the microcontroller waits to ensure the adns- 2610 has powered up and is ready to communicate. the microprocessor then tries to read from location 0x01, status register, and is expecting a value of 0x0b000xxxxx C where x is in dont care state. if it receives this value, it then knows that the communication to the ADNS-2610 is operational. the problem occurs if the adns - 2610 powers up before the microprocessor sets the sck and sdio lines to be outputs and high. the ADNS-2610 sees the raising of the sck as a valid rising edge, and clocks in the state of the sdio as the frst bit of the address (sets either a read or a write depending upon the state). in the case of a sdio low, a read operation will start. when the microprocessor actually begins to send the address, the ADNS-2610 already has the frst bit of an address. when the seventh bit is sent by the microprocessor, the ADNS-2610 has a valid address, and drives the sdio line high within 250 ns (see detail a in figure 21 and figure 22). this results in a bus fght for sdio. since the address is wrong, the data sent back will be incorrect. in the case of sdio high, a write operation will start. the address and data will be out of synchronization, causing the wrong data written to the wrong address. solution there is one way to solve the problem, which is waiting for the serial port timer to time out.
17 if the microprocessor waits at least t sptt from v dd valid, it will ensure that the ADNS-2610 has powered up and the timer has timed out. this assumes that the microprocessor and the adns - 2610 share the same power supply. if not, then the microprocessor must wait for t sptt from ADNS-2610 v dd valid. then when the sck toggles for the address, the ADNS-2610 will be in sync with the microprocessor. resync note if the microprocessor and the ADNS-2610 get out of sync, then the data either written or read from the registers will be incorrect. an easy way to solve this is to use watchdog timer timeout sequence to resync the parts after an incor - rect read. power-up ADNS-2610 has an on-chip internal power-up reset (por) circuit, which will reset the chip when vdd reaches the valid value for the chip to function. soft reset ADNS-2610 may also be given the reset command at any time via the serial i/o port. the timing and transactions are the same as those just specifed for the power-up mode in the previous section. the proper way to perform soft reset on ADNS-2610 is: 1. the microcontroller starts the transaction by sending a write operation containing the address of the confguration register and the data value of 0x80. since the reset bit is set, ADNS-2610 will reset and any other bits written into the confguration register at this time is properly written into the confguration register. after the chip has been reset, very quickly, the ADNS-2610 will clear the reset bit so there is no need for the microcontroller to re-write the confguration register to reset it. 2. the digital section is now ready to go. it takes 3 frames for the analog section to settle. don't care state data = 0x0b000xxxxx address = 0x01 sck sdio v dd >t sptt figure 29. power-up serial port timer sequence. serial port timer timeout figure 0. ADNS-2610 soft reset sequence timing. figure 1. soft reset confguration register writing operation. soft reset will occur when writing 0x80 to the confguration register. clk sck sdio reset occurs 1 a 6 a 5 a 4 a 3 d 5 d 4 d 3 d 2 d 1 d 0 here configuration register address 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 configuration register data writ e sck sdio operation 0
18 programming guide registers the ADNS-2610 can be programmed through registers, via the serial port, and confguration and motion data can be read from these registers. register address notes confguration 0x00 reset, power down, forced awake, etc status 0x01 product id, mouse state of asleep or awake delta_y 0x02 y movement delta_x 0x03 x movement squal 0x04 measure of the number of features visible by the sensor maximum_pixel 0x05 minimum_pixel 0x06 pixel_sum 0x07 pixel data 0x08 actual picture of surface shutter_upper 0x09 shutter_lower 0x0a inverse product 0x11 inverse product id
19 confguration address: 0x00 access: read/write reset value: 0x00 bit 7 6 5 4 3 2 1 0 field c 7 c 6 c 5 c 4 c 3 c 2 c 1 c 0 data type : bit feld usage: the confguration register allows the user to change the confguration of the sensor. shown below are the bits, their default values, and optional values. field name description c 7 reset 0 = no efect 1 = reset the part c 6 power down 0 = normal operation 1 = power down all analog circuitry c 5 C c 1 reserved c 0 forced awake mode 0 = normal, fall asleep after one second of no movement (1500 frames/s) 1 = always awake status address: 0x01 access: read reset value: 0x01 bit 7 6 5 4 3 2 1 0 field id 2 id 1 id 0 reserved reserved reserved reserved awake data type: bit field usage: status information and type of mouse sensor, current state of the mouse. field name description id 2 - id 0 product id (000 for ADNS-2610) reserved reserved for future awake mouse state 0 = asleep 1 = awake
20 delta_y address: 0x02 access: read reset value: 0x00 bit 7 6 5 4 3 2 1 0 field y 7 y 6 y 5 y 4 y 3 y 2 y 1 y 0 data type: eight bit 2s complement number. usage: y movement is counted since last report. absolute value is determined by resolution. reading clears the register. delta_x address: 0x03 access: read reset value: 0x00 bit 7 6 5 4 3 2 1 0 field x 7 x 6 x 5 x 4 x 3 x 2 x 1 x 0 data type: eight bit 2s complement number. usage: x movement is counted since last report. absolute value is determined by resolution. reading clears the register
21 the focus point is important and could afect the squal value. figure 32 shows another setup with various z- heights. this graph clearly shows that the squal value is dependent on focus distance. note: the data is obtained by getting multiple readings over diferent heights. squal address: 0x04 access: read reset value: 0x00 bit 7 6 5 4 3 2 1 0 field sq 7 sq 6 sq 5 sq 4 sq 3 sq 2 sq 1 sq 0 data type: upper 8 bits of a 9-bit integer. usage: squal (surface quality) is a measure of the number of features visible by the sensor in the current frame. number of features = squal register value x 2. the maximum value is 255. since small changes in the current frame can result in changes in squal, variations in squal when looking at a surface are expected. the graph below shows 250 sequentially acquired squal values, while a sensor was moved slowly over white paper. squal is nearly equal to zero when there is no surface below the sensor. 1.50 1.25 1.00 0.75 0.50 0.25 0 normalized squal v alue del ta from nominal focus (mm) figure 32. typical mean squal vs. z (white paper). -1.0 -0.6 -0.2 0.2 0.6 1.0 3 3 ? + x x x
22 maximum_pixel address: 0x05 access: read reset value: 0x00 bit 7 6 5 4 3 2 1 0 field 0 0 mp 5 mp 4 mp 3 mp 2 mp 1 mp 0 data type: six bit number. usage: maximum pixel value in current frame. minimum value = 0, maximum value = 63. the maximum pixel value may vary from frame to frame. shown below is a graph of 250 sequentially acquired maximum pixel values, while the sensor was moved slowly over white paper. minimum_pixel address: 0x06 access: read reset value: 0x3f bit 7 6 5 4 3 2 1 0 field 0 0 mp 5 mp 4 mp 3 mp 2 mp 1 mp 0 data type: six bit number. usage: minimum pixel value in current frame. minimum value = 0, maximum value = 63. the minimum pixel value may vary from frame to frame. min pixel on white paper test number 64 48 32 16 0 1 1 6 3 1 4 6 6 1 7 6 9 1 106 121 136 151 166 181 196 211 226 241 256 min pixel max pixel on white paper test number 64 48 32 16 0 1 1 6 3 1 4 6 6 1 7 6 9 1 106 121 136 151 166 181 196 211 226 241 256 max pixel
2 pixel_sum address: 0x07 access: read reset value: 0x00 bit 7 6 5 4 3 2 1 0 field ps 7 ps 6 ps 5 ps 4 ps 3 ps 2 ps 1 ps 0 data type: upper 8 bits of a 15-bit unsigned integer. usage: this register is used to fnd the average pixel value. it reports the upper 8 bits of a 15-bit unsigned integer, which sums all 324 pixels in the current frame. it may be described as the full sum divided by 128. the formula to calculate the average pixel value is as below: average pixel = register value x 128 / 324= pixel_sum x 0.395 the maximum register value is 159 (63 x 324 / 128 truncated to an integer). the minimum is 0. the pixel sum value may vary from frame to frame. pixel data address: 0x08 access: read/write reset value: 0x00 bit 7 6 5 4 3 2 1 0 field sof data_valid pd 5 pd 4 pd 3 pd 2 pd 1 pd 0 data type: two status bits, six bit pixel data. usage: digital pixel data. minimum value = 0, maximum value = 63. any writes to this register resets the pixel hardware so that the next read from the pixel data register will read pixel #1 and the startofframe bit will be set. subsequent reads will auto increment the pixel number. to dump a complete image, set the led to forced awake mode, write anything to this register, then read 324 times where the datavalid bit is set. on the 325th read, the startofframe bit will be set indicating that we have completed one frame of pixels and are starting back at pixel 1. it takes at least 324 frames to complete an image as we can only read 1 pixel per frame. the pixel hardware is armed with any read or write to the pixel data register and will output pixel data from the next available frame. so, if you were to write the pixel data register, wait 5 seconds then read the pixel data register; the reported pixel data was from 5 seconds ago. field name description sof start of frame 0 = not start of frame 1 = current pixel is number 1, start of frame data_valid there is valid data in the frame grabber pd 5 Cpd 0 six bit pixel data
24 pixel map (sensor is facing down, looking through the sensor at the surface) first pixel last pixel
25 pixel dump pictures the following images are the output of the pixel data command. the data ranges from 0 for complete black, to 63 for complete white. an internal agc circuit adjusts the shutter value to keep the brightest feature (max pixel) in the mid 50s. (a) white paper (b) manila folder (c) burl formica (d) usaf test chart
26 note: this graph is obtained by getting multiple readings over diferent heights. shutter_upper address: 0x09 access: read reset value: 0x01 bit 7 6 5 4 3 2 1 0 field s 15 s 14 s 13 s 12 s 11 s 10 s 9 s 8 shutter_lower address: 0x0a access: read reset value: 0x00 bit 7 6 5 4 3 2 1 0 field s 7 s 6 s 5 s 4 s 3 s 2 s 1 s 0 data type: sixteen bit word. usage: units are clock cycles; default value is 0x0100 hex . read shutter_upper frst, then shutter_lower. they should be read consecutively. the sensor adjusts the shutter to keep the average and maximum pixel values within normal operating ranges. the shutter value may vary with every frame. each time the shutter changes, it changes by 1/16 of the current value. 1.50 1.25 1.00 0.75 0.50 0.25 0 normalized shutter v alue (counts) dist ance from nominal focus (mm) figure 33. typical mean shutter vs. z (white paper). -1.0 -0.6 -0.2 0.2 0.6 1.0 3 3 ? + x x x
for product information and a complete list of distributors, please go to our web site: www.avagotech.com avago, avago technologies, and the a logo are trademarks of avago technologies in the united states and other countries. data subject to change. copyright ? 2005-2008 avago technologies. all rights reserved. obsoletes 5988-9774en av02-1184en - september 4, 2008 the maximum value of the shutter is dependent upon the clock frequency. the formula for the maximum shut - ter value is: clock freq max shutter value = C 3476 1500 frames/second max shutter shutter decimal hex upper lower 1512 12397 0x306d 30 6d default max shutter for a clock frequency of 24 mhz, the following table shows the maximum shutter value. 1 clock cycle is 41.67 nsec. --> ordering information specify part number as follows: ADNS-2610 = 8-pin staggered dual inline package (dip), 40 per tube. inverse_product address: 0x11 access: read reset value: 0xff bit 7 6 5 4 3 2 1 0 field reserved reserved reserved reserved ip 3 ip 2 ip 1 ip 0 data type: 4 bit number. usage: status information and type of mouse sensor field name description reserved reserved for future use ip 3 -ip 0 inverse product id (x1111b or xfh)

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